In recent years, with the increasing demand for miniaturization and multi-functionalization of mobile phones, various digital electronic devices and the like, there has also been a strong demand for miniaturization and multi-functionalization of electronic components such as a semiconductor IC element used in those devices and of a printed wiring board on which such components are mounted. In order to meet such a demand, development of various multilayer wiring board technologies has been underway.
A first example of the conventional multilayer wiring board technologies is an EWLP (Embedded Wafer Level Package) technology as disclosed in Patent Document 1. This technology is for forming a package substrate having a multilayer structure by disposing a semiconductor chip, for example, on a support plate and sequentially building up an insulating layer, a metal column for an interlayer via and a wiring metal layer thereon.
Moreover, a second example is a technology as disclosed in Patent Document 2. In the technology, a number of wiring boards are prepared each of which has a wiring conductive layer provided on one surface of an insulating substrate and an adhesive layer provided on the other surface thereof and is provided with a conductive via (through-electrode) made of a conductive paste and serving as an interlayer conductive via. Then, these wiring boards are laminated with the adhesive layers interposed therebetween, and collectively heated and pressure-bonded so as to form a multilayer wiring board.
Patent Document 1: Japanese Patent Application Publication No. 2004-95836
Patent Document 2: Japanese Patent Application Publication No. 2003-318546
Patent Document 3: Japanese Patent Application Publication No. 2001-102754
Patent Document 4: Japanese Patent Application Publication No. 2005-45187